1. Technical Field
The present invention relates to a semiconductor integrated circuit device, and, in particular, to a semiconductor integrated circuit device which is provided with a standard logic cell having a multi-height structure.
2. Background Art
As a method of forming a semiconductor integrated-circuit on a semiconductor substrate, a standard logic cell method has been known. The standard logic cell method is a method of designing a Large-Scale Integration (LSI) chip by providing a basic unit (for example, an inverter, a latch, a flip-flop, a full adder, or the like) having a specific logical function as a standard logic cell in advance, disposing a plurality of standard logic cells on a semiconductor substrate and connecting between the standard logic cells using metal wirings.
Recently, with accelerated demands for high-speed and small area in a semiconductor integrated-circuit, a method of applying a double height structure to a standard logic cell (for example, refer to Japanese Patent Unexamined Publication No. 7-249747) has been known as a method of enabling a transistor disposition region, which occupies the interior of a cell, to be effectively enlarged. FIG. 12 illustrates the schematic layout of a semiconductor integrated circuit device disclosed in Japanese Patent Unexamined Publication No. 7-249747. The semiconductor integrated circuit device includes standard logic cell 901 which has a single height structure (hereinafter, denoted by “single height cell”), and standard logic cell 902 which has a double height structure (hereinafter, denoted by “double height cell”). The cell height of single height cell 901 is uniform, and the cell width of single height cell 901 can be enlarged. Double height cell 902 has a cell height which is twice as high as the cell height of single height cell 901. Since double height cell 902 can enlarge the channel width of a transistor, which occupies the interior of a cell, by commoditizing a P-well region (or an N-well region), the drive capability of the transistor can be improved without enlarging the cell width, unlike single height cell 901.
Since a region where wiring is possible can be enlarged by changing the structure of the standard logic cell from a single height structure to the double height structure, the degree of the freedom of the disposition of contacts or wirings can be increased. As a result, M1 wiring which extends in the X-axis direction (cell width direction) can be disposed. A wiring path can be also circumvented using M2 wiring. M1 wiring is a wiring which is formed on a first metal wiring layer (that is, a metal wiring layer which is the nearest to a semiconductor substrate) disposed on the upper layer of the semiconductor substrate, and M2 wiring is a wiring which is formed on a second metal wiring layer (that is, a metal wiring layer which is the second nearest to the semiconductor substrate) disposed on the upper layer of the first metal wiring layer. M2 wiring extends in the Y-axis direction (cell height direction).
The circumvention of the wiring path using M2 wiring, which extends in the Y-axis direction, will be described with reference to FIG. 13. FIG. 13 is an example of the layout of cell region 903 surrounded by the dotted-line of double height cell 902 shown in FIG. 12. Double height cell 902 includes three power wirings which extend in parallel with X-axis direction, and the cell height of double height cell 902 corresponds to 18 tracks. Cell region 903 corresponds to a part of the cell region between any one of power wiring WP81 of the power wirings of both ends and center power wiring WP82, and the separation distance between power wirings WP81 and WP82 corresponds to 9 tracks (that is, half of the cell height). Generally, the cell height of the standard logic cell is expressed using the number of wirings (that is, the number of wiring tracks) which can be added in the standard logic cell and which extend in the X-axis direction.
As shown in FIG. 13, when M1 wiring W800 which extends in the X-axis direction is disposed between PMOS transistor PM9 and NMOS transistor NM9, it is difficult to electrically connect each of the drain regions of PMOS transistor PM9 and NMOS transistor NM9 using M1 wiring. The drain region of PMOS transistor PM9 is electrically connected to M1 wiring W801 through contact C801, the drain region of NMOS transistor NM9 is electrically connected to M1 wiring W802 through contact C802, and each of M1 wirings W801 and W802 is electrically connected to M2 wiring W901 through vias V901 and V902.
In double height cell, M2 wiring which extends in the Y-axis direction is used in order to circumvent the wiring path. Not only in the double height cell but also in a standard logic cell which includes a multi-height structure, M2 wiring which extends in the Y-axis direction (cell height direction) is used in order to circumvent the wiring path. The standard logic cell which includes the multi-height structure is the standard logic cell which has a cell height n times (n is an integer number which is equal to or greater than 2) higher than the cell height of a single height cell.